The present invention relates generally to a uniquely designed solid state, electrically operated memory element. More specifically, the present invention relates to programmable resistance memory elements.
Programmable resistance memory elements formed from materials that can be programmed to exhibit at least a high or low stable resistance state are known in the art. Such programmable resistance elements may be programmed to a high resistance state to store, for example, a logic ONE data bit. As well, they may be programmed to a low resistance state to store, for example, a logic ZERO data bit.
One type of material that can be used as the memory material for programmable resistance elements is phase change material. Phase change materials may be programmed between a first structural state where the material is generally more amorphous (less ordered) and a second structural state where the material is generally more crystalline (more ordered). The term xe2x80x9camorphousxe2x80x9d, as used herein, refers to a condition which is relatively structurally less ordered or more disordered than a single crystal and has a detectable characteristic, such as high electrical resistivity. The term xe2x80x9ccrystallinexe2x80x9d, as used herein, refers to a condition which is relatively structurally more ordered than amorphous and has lower electrical resistivity than the amorphous state.
The concept of utilizing electrically programmable phase change materials for electronic memory applications is disclosed, for example, in U.S. Pat. Nos. 3,271,591 and 3,530,441, the contents of which are incorporated herein by reference. The early phase change materials described in the ""591 and ""441 Patents were based on changes in local structural order. The changes in structural order were typically accompanied by atomic migration of certain species within the material. Such atomic migration between the amorphous and crystalline states made programming energies relatively high.
The electrical energy required to produce a detectable change in resistance in these materials was typically in the range of about a microjoule. This amount of energy must be delivered to each of the memory elements in the solid state matrix of rows and columns of memory cells. Such high energy requirements translate into high current carrying requirements for the address lines and for the cell isolation/address device associated with each discrete memory element.
The high energy requirements for programming the memory cells described in the ""591 and ""441 patents limited the use of these cells as a direct and universal replacement for present computer memory applications, such as tape, floppy disks, magnetic or optical hard disk drives, solid state disk flash, DRAM, SRAM, and socket flash memory. In particular, low programming energy is important when the EEPROMs are used for large-scale archival storage. Used in this manner, the EEPROMs would replace the mechanical hard drives (such as magnetic or optical hard drives) of present computer systems. One of the main reasons for this replacement of conventional mechanical hard drives with EEPROM xe2x80x9chard drivesxe2x80x9d would be to reduce the power consumption of the mechanical systems. In the case of lap-top computers, this is of particular interest because the mechanical hard disk drive is one of the largest power consumers therein. Therefore, it would be advantageous to reduce this power load, thereby substantially increasing the operating time of the computer per charge of the power cells. However, if the EEPROM replacement for hard drives has high programming energy requirements (and high power requirements), the power savings may be inconsequential or at best unsubstantial. Therefore, any EEPROM which is to be considered a universal memory requires low programming energy.
The programming energy requirements of a programmable resistance memory element may be reduced in different ways. For example, the programming energies may be reduced by the appropriate selection of the composition of the memory material. An example of a phase change material having reduced energy requirements is described in U.S. Pat. No. 5,166,758, the disclosure of which is incorporated by reference herein. Other examples of memory materials are provided in U.S. Pat. Nos. 5,296,716, 5,414,271, 5,359,205, and 5,534,712 disclosures of which are all incorporated by reference herein.
The programming energy requirement may also be reduced through the appropriate modification of the electrical contacts used to deliver the programming energy to the memory material. For example, reduction in programming energy may be achieved by modifying the composition and/or shape and/or configuration (positioning relative to the memory material) of the electrical contacts. Examples of such xe2x80x9ccontact modificationxe2x80x9d are provided in U.S. Pat. Nos. 5341,328, 5,406,509, 5,534,711, 5,536,947, 5,687,112, 5,933,365 all of which are incorporated by reference herein. Examples are also provided in U.S. patent application Ser. No. 09/276,273 the disclosure of which is incorporated herein by reference. Examples are also provided in U.S. patent application Ser. No. 09/620,318 the disclosure of which is incorporated herein by reference. More examples are provided in U.S. patent application Ser. No. 09/677,957 the disclosure of which is incorporated herein by reference. The present invention is directed to novel structures of a programmable resistance memory element and methods for making these structures.
One aspect of the present invention is a method for making a pore, comprising: providing a layer of a first material; forming a layer of a second material on the layer of the first material; forming a layer of a third material on the second material; forming a sidewall surface in the layer of the third material; forming a layer of a forth material on the layer of the third material; removing a portion of the layer of the forth material; and removing a portion of the layer of the second material to define the pore in the layer of the second material.
Another aspect of the present invention is a method of fabricating a pore, comprising: providing a layer of a first material; applying a layer of a second material onto the layer of the first material; applying a layer of a third material onto the layer of the second material; removing a portion of the layer of the third material to form an opening in the layer of the third material; applying a layer of a forth material into the opening; removing a portion of the layer of the forth material; and removing a portion of the layer of second material to define a pore in the layer of second material.
Another of aspect of the present invention is a method of fabricating a pore, comprising: providing a layer of a first material; forming a layer of a second material on the layer of the first material; forming a layer of a third material on the layer of the second material; removing a portion of the layer of the third material to define an opening in the layer of the third material; forming a sidewall spacer on a peripheral portion of the opening; and removing a portion of the layer of the second material to define the pore in the layer of the second material.